229 235 240 245 250 255 260 265 270 275 280 285 290 295 300 304 152 150 145 140 135 130 125 120 115 110 105 100 95 90 85 80 77 228 225 220 215 210 205 200 195 190 185 180 175 170 165 160 155 153 10 15 20 25 30 35 40 45 50 55 60 65 70 75 76 gnd gnd gnd v dd (+3.3v) v dd (+3.3v) gnd gnd v dd (+3.3v) gnd v dd (+3.3v) gnd gnd v dd (+3.3v) gnd v dd (+3.3v) gnd gnd v dd (+3.3v) gnd gnd gnd { v dd (+3.3v) gnd v dd (+3.3v) gnd v dd (+3.3v) gnd gnd v dd (+3.3v) gnd v dd (+3.3v) gnd v dd (+3.3v) gnd v dd (+3.3v) gnd v dd (+3.3v) gnd gnd gnd gnd gnd { v dd (+3.3v) ********** c-mos inner error correction decoder - top view - CXD8808R(1/4) 5 1 il08 230
CXD8808R (2/4) pin no. i/o signal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 signal i/o no. pin signal i/o no. pin signal i/o no. pin signal i/o no. pin 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 i i i i i i ? i i i i i ? o o o o o i/o ? i/o i/o i/o i/o i/o ? i/o i/o i i i i ? i i i i i i i i i i ? o o o o o o ? o o o o i ? i o o o o o ? i i i i i ? i i i i i i i i i i i i ? i i i i i ? ? i i ? i i ? o i i i o ? o o o o o o ? o o o o o o o o o o ? o i/o i/o i/o i/o i/o ? i/o i/o i/o o i ? o o o o o o ? o o o o o ? o o o o o o i/o i/o i/o i/o i/o i/o ? i/o i/o i/o i/o o ? o o o o o o ? o o o o o ? o o o o o o ? o o o o o o o o o o ? i/o i/o i/o i/o i/o i/o ? i/o i/o i/o i/o i/o ? i/o i/o i/o i/o i/o i/o ? i/o i/o i/o i/o i/o ? i/o i/o i/o i/o i/o i/o o o o o o o ? o o o o o ? o o o o o o ? i o i/o i/o i/o ? i/o i/o i/o i/o i/o o ? o o o o o o o o o o ? o o o o o o ? o ? i i o ? i i ? i i ? ? i i i i i ? i i i i i i advdb4 cnfdb0 cnvdb1 cnfdb2 cnfdb3 cnfdb4 gnd recdb0 recdb1 recdb2 recdb3 recdb4 fs5f0 fs5f1 fs5f2 fsprty rst sysio0 gnd sysio1 sysio2 sysio3 sysio4 sysio5 v dd dhacsw dhbdsw advda0 advda1 advda2 advda3 advda4 gnd cnfda0 cnfda1 cnfda2 cnfda3 cnfda4 recda0 recda1 recda2 recda3 recda4 advswa advcka gnd cnfcka tgtp1 tgtp2 tgtp3 mema1d1 mema1d2 mema1d3 mema1d4 mema1d5 mema1d6 mema1d7 mawe wecn1 gnd ma2ad0 ma2ad1 ma2ad2 ma2ad3 ma2ad4 ma2ad5 ma2ad6 ma2ad7 ma2ad8 ma2ad9 ma2ad10 gnd dd v dd v dd v vadata4 gnd vadata5 vadata6 vadata7 vadata8 f5 auaxs auch ausync aust vaprity gnd maxb stlbd0 stlbd1 stlbd2 stlbd3 stlbd4 stlbd5 stlbd6 stlbd7 stlbd8 maxa gnd v dd mb2ad2 mb2ad1 mb2ad0 gnd wecn2 mbwe memb1d7 memb1d6 memb1d5 memb1d4 memb1d3 memb1d2 memb1d1 memb1d0 mb1ad16 gnd mb1ad15 mb1ad14 mb1ad13 mb1ad12 mb1ad11 mb1ad10 dd v sysio6 sysio7 gctl0 gctl1 gctl2 gctl3 gnd gctl4 gctl5 strb scs stat0 stat1 chipid0 chipid1 gtest rst3 gnd revo jumpo shtlo v dd cnfswa xmm mck gnd recswa reccka gnd wst1 refv refvp sytest mwr1 ma1ad0 ma1ad1 ma1ad2 ma1ad3 ma1ad4 ma1ad5 gnd dd v dd v dd v ma2ad11 ma2ad12 ma2ad13 ma2ad14 ma2ad15 ma2ad16 mema2d0 mema2d1 mema2d2 mema2d3 mema2d4 mema2d5 gnd mema2d6 mema2d7 drefio wrio vprity vblk vsync vvst v dd stlad0 stlad1 stlad2 stlad3 stlad4 stlad5 stlad6 stlad7 stlad8 memb2d7 memb2d6 gnd memb2d5 memb2d4 memb2d3 memb2d2 memb2d1 memb2d0 dd v mb1ad9 mb1ad8 mb1ad7 mb1ad6 gnd mb1ad5 mb1ad4 mb1ad3 mb1ad2 mb1ad1 mb1ad0 mwr2 gnd chsl sttp wst2 gnd recckb recswb gnd pck ms cnfswb rev jump v dd dd v dd v seg0 seg1 f0 trref nosigo acsy bdsy rst1 gnd rst2 acef bdef mon v dd ma1ad6 ma1ad7 ma1ad8 ma1ad9 ma1ad10 ma1ad11 ma1ad12 ma1ad13 ma1ad14 ma1ad15 gnd ma1ad16 mema1d0 vdata0 vdata1 vdata2 gnd vdata3 vdata4 vdata5 vdata6 vdata7 vdata8 vadata0 vadata1 vadata2 vadata3 dd v mb2ad16 mb2ad15 mb2ad14 mb2ad13 mb2ad12 mb2ad11 gnd mb2ad10 mb2ad9 mb2ad8 mb2ad7 mb2ad6 mb2ad5 mb2ad4 mb2ad3 v dd ictest cnfckb gnd advckb advswb advdb0 advdb1 advdb2 advdb3 (v =+3.3v) dd
CXD8808R (3/4) input advcka, advckb advda0?dvda4, advdb0?dvdb4 advswa, advswb chipid0, chipid1 chsl cnfcka, cnfckb cnfda0?nfda4, cnfdb0?nfdb4 cnfswa, cnfswb gctl0?ctl5, gtest, ictest jump mck ms pck reccka, recckb recda0?ecda4, recdb0?ecdb4 recswa, recswb refv refvp rev rst1, rst2, rst3 scs stat0, stat1 strb sttp, sytest, tgtp1?gtp3, xmm wecn1, wecn2 output acef, bdef acsy, bdsy auaxs auch aust ausync dhacsw,dhbdsw f0 f5 fs5f0?s5f2 fsprty jumpo ma1ad0?a1ad16, mb1ad0?b1ad16 ma2ad0?a2ad16, mb2ad0?b2ad16 mawe, mbwe mon mwr1, mwr2 nosigo revo seg0, seg1 shtlo trref vadata0?adata8 vaprity vblk vdata0?data8 vprity vsync vvst wst1, wst2 ; advance a/c, b/d ch clock ; advance a/c, b/d ch data ; advance a/c, b/d ch head switching ; system control interface chip id ; 1?ch/5?ch select ; confidence a/c, b/d ch clock ; confidence a/c, b/d ch data ; confidence a/c, b/d ch head switching ; test pin ; dt jump ; 13.5 mhz clock ; shuttle interface control ; 13.5 mhz program play clock ; record a/c, b/d ch clock ; record a/c, b/d ch data ; record a/c, b/d ch head switching signal ; reference vd ; program play reference vd ; reverse mode input ; ic reset 1.2.3 ; system control interface chip select ; system control interface states ; system control interface strobe ; test pin ; a/c, b/d ch field memory data enable ; a/c, b/d ch error flag ; a/c, b/d ch sync ; audio auxiliary data sync pulse ; audio channel pulse ; audio field start pulse ; audio sync pulse ; test pin ; field id ; 526/60 audio 0 field pulse ; audio 5 field sequence ; audio 5 field sequence parity ; dt jump states ; a/c, b/d ch field memory 1 address ; a/c, b/d ch field memory 2 address ; a/c, b/d ch field memory write enable ; test pin ; a/c, b/d ch field memory write/read control ; no signal states ; reverse states ; segment number ; shuttle states ; track sync pulse ; audio data and b/d ch video data ; audio video data parity ; video ecc block pulse ; a/c ch video data ; video data parity ; video sync pulse ; video field start pulse ; test pin
CXD8808R (4/4) input/output drefio maxa, maxb mema1d0?ema1d7, memb1d0?emb1d7 mema2d0?ema2d7, memb2d0?emb2d7 stlad0?tlad8, stlbd0?tlbd8 sysio0?ysio7 wrio ; reference vd synchronous interface ; a/c, b/d ch shuttle old flag interface ; a/c, b/d ch field memory 1 data ; a/c, b/d ch field memory 2 data ; a/c, b/d ch shuttle data interface ; system control interface data ; write/read control synchronous interface
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